package SimpleLACore

import chisel3._

class SimpleLACoreTopSRAM extends Module {
  val io = IO(new Bundle {
    val ipi = Input(Bool())
    val interrupt = Input(UInt(8.W))
    val debug_pc = Output(UInt(32.W))
    val debug_wen = Output(UInt(4.W))
    val debug_wnum = Output(UInt(5.W))
    val debug_wdata = Output(UInt(32.W))
    val inst = Flipped(new SRAMIO)
    val data = Flipped(new SRAMIO)
  })
  val core = Module(new SimpleLACore)
  core.io.ipi := io.ipi
  core.io.interrupt := io.interrupt
  io.debug_pc := core.io.debug.pc
  io.debug_wen := core.io.debug.wen
  io.debug_wnum := core.io.debug.wnum
  io.debug_wdata := core.io.debug.wdata
  val iCache = Module(new SimpleCacheSRAM)
  val dCache = Module(new SimpleCacheSRAM)
  io.inst <> iCache.io.ram
  io.data <> dCache.io.ram
  core.io.inst <> iCache.io.core
  core.io.data <> dCache.io.core
}
